The present invention relates generally to methodologies for reducing the common mode noises generated by two-level rectifier/inverter variable frequency drive (VFD) systems. This invention more particularly relates to modulation techniques for common mode noise reduction.
Referring to FIG. 1, an exemplary two-level rectifier/inverter variable frequency drive (VFD) system is shown that includes a three phase voltage source, a rectifier, a three phase inverter and a load (e.g., a motor). The rectifier may be either a diode type (i.e., constructed using diodes) or an active type (i.e., a boost type including controllable switching devices that is controlled via pulse width modulation (PWM) or the like). Where the rectifier is active, the rectifier typically includes six switching devices (e.g., solid state semiconductor-based switching elements such as silicon-controlled rectifiers (SCRs), gate turn-off thyristors (GTOs), gate commutated thyristors (GCTs), insulated gate bipolar transistors (IGBTs)) that convert three phase input power to DC voltage across the two lines that connect the rectifier to the inverter.
In a three phase system the inverter typically includes six switching devices that link the DC lines to the three phase load. By switching the inverter switches on and off, the three phases of the load are linked to the positive and negative DC lines. By switching the inverter switches in a controlled fashion, the voltages and currents on the lines linked to the load can be controlled so that variable frequency power is delivered to the load.
To generate switch control signals, many systems employ pulse PWM techniques where modulating waveforms (e.g., sinusoidal or other) are generated for each system phase and are compared to high frequency carrier signals (e.g., often thought of as high frequency saw tooth waveforms). Based on the comparisons, switch control signals are generated that turn the active rectifier and inverter switches on and off. Several PWM schemes are commonly employed and are well known in the drives industry including space vector PWM (SVPWM) and discontinuous PWM (DPWM), where the different schemes employ differently shaped modulating waveforms.
Referring to FIG. 2, a PWM diagram is illustrated that includes eight different vectors V0, V1, V2, V3, V4, V5, V6 and V7 where each vector is associated with a unique switching state of the top three switches (e.g., G1, G3 and G5) in the inverter of FIG. 1 where a “1” indicates that an associated switch is closed or on and a “0” indicates that an associated switch is open or off. For instance, for vector V1, the (100) label indicates that switches G1, G3 and G5 are on, off and off, respectively. The bottom switch states are the inverse of the top switch states. For instance, when the state of switch G1 is “1” (i.e., on), the state of associated bottom switch G2 is “0” (i.e., off).
As well known in the drives industry, as the switches of either an active rectifier or an inverter are turned on and off, under certain circumstances, common-mode voltages (CMVs) are generated that appear in the output phases of the motor drive and hence on the motor windings. CMV pulses cause CMV dv/dts which in turn cause common mode current (CMC) spikes. The number of CMC spikes is equal to the number of CMV dv/dt steps. Referring still to FIG. 1, the CMV appears between the neutral point “n” of the motor windings and ground “g”. CMV and associated CMC have been known to reach levels beyond motor winding insulation ratings and can result in undesirable bearing currents. Consequently, CMV and CMC often reduce system performance at a minimum and have been known to damage motor components.
Referring again to FIG. 1, CMV can be expressed by the following equations:CMV=Vng=Vno+Vog  Eq. 1Vno=(Vuo+Vvo+Vwo)/3  Eq. 2Vog=−(Vao+Vbo+Vco)/3  Eq. 3
As to diode rectifier/inverter systems, the frequency and amplitude of voltage Vog is determined by the frequency of the power supply linked to the front end of the converter. For instance, where the AC power supply provides 60 Hz power, the three phase rectifier generates voltage Vog having a positive 180 Hz ripple waveform and a negative 180 Hz ripple waveform and therefore the CMV likewise has a 180 Hz ripple.
Another portion of the CMV in a diode rectifier/inverter system, the Vno portion, is related to or caused by inverter modulation and has amplitudes as shown in Table 1 where the vectors (i.e., V0, V1, V2, etc.) are space vectors as shown in FIG. 2.
TABLE 1VectorState (G1, G3, G5)VuoVvoVwoVnoV0(0, 0, 0)−Vdc/2−Vdc/2−Vdc/2−Vdc/2V1(1, 0, 0)  Vdc/2−Vdc/2−Vdc/2−Vdc/6V2(1, 1, 0)  Vdc/2  Vdc/2−Vdc/2  Vdc/6V3(0, 1, 0)−Vdc/2  Vdc/2−Vdc/2−Vdc/6V4(0, 1, 1)−Vdc/2  Vdc/2  Vdc/2  Vdc/6V5(0, 0, 1)−Vdc/2−Vdc/2  Vdc/2−Vdc/6V6(1, 0, 1)  Vdc/2−Vdc/2  Vdc/2  Vdc/6V7(1, 1, 1)  Vdc/2  Vdc/2  Vdc/2  Vdc/2
According to table 1, instantaneous values of voltage Vno can be expressed as:
                              V          no                =                  {                                                                      ±                                                            V                      dc                                        2                                                                                                for                  ⁢                                                                          ⁢                                      V                    0                                    ⁢                                                                          ⁢                  and                  ⁢                                                                          ⁢                                      V                    7                                                                                                                        ±                                                            V                      dc                                        6                                                                                                for                  ⁢                                                                          ⁢                  other                  ⁢                                                                          ⁢                  states                                                                                        Eq        .                                  ⁢        4            
Referring to FIG. 3, a CMV (Vno) waveform and an associated CMC waveform are illustrated that result during one switching period when standard SVPWM control is employed. As shown, at each of times t1, t2, t3, t4, t5 and t6 a dv/dt occurs which results in current spikes ands the peak to peak value of the CMV is Vdc. FIG. 4 shows an FFT spectrum plot of CMC corresponding to FIG. 3. FIGS. 5 and 6 include plots similar to those shown in FIGS. 3 and 4, respectively, albeit where DPWM was employed instead of SVPWM.
In an attempt to reduce CMV and CMC, some modified modulators for diode rectifier/inverter systems have been developed that modify inverter switching patterns so that zero switching states (V0 and V7) are virtually (as opposed to actually) created by using two active vectors that are 180 degree out of phase. By virtually creating the zero switching states the peak-to-peak amplitude of the CMV can be significantly reduced. These modified modulators are based on direct-digital SVPWM where dwell-times must be calculated in real-time for optimal performance.
As to active rectifier/inverter systems, there are eight available output voltage vectors (V0-V7) for both the boost rectifier and inverter according to the eight different switching states depicted in FIG. 2. The possible CMV states for the various output voltage vectors of an active rectifier/inverter system are summarized in Table 2.
TABLE 2Inverter Output Voltage VectorV1, V3,V2, V4,V5V6V0V7BoostV1, V3,0Vdc/3−Vdc/32 Vdc/3RectifierV5OutputV2, V4,−Vdc/30−2 Vdc/3Vdc/3VoltageV6VectorV0Vdc/32 Vdc/30VdcV7−2 Vdc/3−Vdc/3−Vdc0In case of an asynchronous switching sequence or a different switching frequency between the boost rectifier and inverter, a CMV with peak-to-peak amplitude of 2Vdc can occur.
Nevertheless, it is well know that the CMV peak-to-peak amplitude generated by boost rectifier/inverter systems can be restricted to be no more than 1.33Vdc by synchronizing the switching sequence between the rectifier and inverter stages of the system. Unfortunately synchronization of the switching sequences is not easy to facilitate when the switching frequency of the boost rectifier is different than the frequency of the inverter.
Some modified modulators for active rectifier/inverter systems have been developed that can further reduce the number of CMV pulses in a three-phase system where synchronized switching is realized. In at least some schemes it is possible to eliminate one CMV pulse in every switching period by shifting the active voltage vectors of the inverter to align with those of the boost rectifier. Compared with the conventional three-phase SVPWM scheme, this proposed method can reduce the total number of CMV pulses by one-third.
Unfortunately, this vector shifting SVPWM control scheme cannot be applied to diode rectifier/inverter systems. Where this control scheme is used with an active rectifier/inverter system, for optimal performance, the dwell-time must be calculated in real-time to shift the active voltage vectors and the shifts should be performed in every switching period. Calculating dwell times in real time requires excessive dedicated computing power.
Therefore, it would be advantageous to have a system wherein common mode voltages can be reduced in rectifier/inverter systems generally without requiring dwell time calculations.